Inactive JEDEC outline as of 1996. For other assistance, including website or account help, contact JEDEC by email here. Package Symbol Type Package Types Old New Pin Count Surface Mounting Type Ceramic HQFP FS FB 208, 256. The Joint Electron Device Engineering Council (JEDEC) was established to provide recognized technical standards for a wide range of applications, from how to handle electronic packages and defining package outline drawings, to the methods used to characterize performance, including thermal. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866, ANSI/ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL, EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (5.1), FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES, GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD, HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST), JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES, JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NONHERMETIC SURFACE-MOUNT DEVICES, JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - COMPONENT LEVEL, PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. Item 11.2-962. This roster provides information on the JEDEC office staff and the various JEDEC committees and chairs, with their company affiliations. JEDEC specifications are available at: JEDEC. The pyramid in Figure 1 illustrates the hierarchy for EIA/JEDEC testing procedures and The committees within JEDEC are: JC10 Terms, Definitions, and Symbols JC-11 Mechanical (Package Outline) Standardization JC-13 Government Liaison JC-14 Quality and Reliability of Solid-State Products Apply Annex (Annexes for JESD21-C) filter, Apply DIMM-LABEL (4.19 DIMM Label) filter, Apply DRAM (3.9 Dynamic Random Access Memory) filter, Apply EEPROM (3.5 Electrically Erasable Programmable Read Only Memory) filter, Apply EPROM (3.4 Erasable Programmable Read Only Memory) filter, Apply IPC/JEDEC (Joint IPC/JEDEC Standard) filter, Apply J-STD- (Joint IPC/JEDEC Standards) filter, Apply JEB (JEDEC Engineering Bulletins) filter, Apply MCP (3.12 Multi Chip Packages) filter, Apply MO- (Microelectronic Outlines) filter, Apply MODULE (4, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7 Modules) filter, Apply MPDRAM (3.10 Multiport Dynamic Random Access Memory) filter, Apply MS- (Microelectronic Standards) filter, Apply NVRAM (3.6 Nonvolatile Random Access Memory) filter, Apply PR (Preliminary Release for JESD21-C) filter, Apply PROM (3.3 Programmable Read Only Memory) filter, Apply PSRAM (3.8 Pseudostatic Random Access Memory) filter, Apply RDF (Registration Data Format) filter, Apply SDRAM (3.11 Synchronous Dynamic Random Access Memory) filter, Apply SPD (4.1.2 Serial Presence Detect) filter, Apply SPP- (Standard Practices and Procedures) filter, Apply SRAM (3.7 Static Random Access Memory) filter, Apply TENTSTD (Tentative Standards) filter, Wide Bandgap Power Semiconductors: GaN, SiC, Order JEDEC Standard Manufacturer's ID Code, JC-14: Quality and Reliability of Solid State Products, JC-15: Thermal Characterization Techniques for Semiconductor Packages, JC-64: Embedded Memory Storage & Removable Memory Cards, JC-70: Wide Bandgap Power Electronic Conversion Semiconductors, JEDEC Awards: Dr. Joo Sun Choi, Samsung Electronics, JEDEC Quality & Reliability Task Group in China, DRAM (3.9 Dynamic Random Access Memory) (6), EEPROM (3.5 Electrically Erasable Programmable Read Only Memory) (4), EPROM (3.4 Erasable Programmable Read Only Memory) (3), MODULE (4, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7 Modules) (119), MPDRAM (3.10 Multiport Dynamic Random Access Memory) (5), NVRAM (3.6 Nonvolatile Random Access Memory) (2), PR (Preliminary Release for JESD21-C) (8), PROM (3.3 Programmable Read Only Memory) (3), PSRAM (3.8 Pseudostatic Random Access Memory) (1), SDRAM (3.11 Synchronous Dynamic Random Access Memory) (16), SPP- (Standard Practices and Procedures) (25), SRAM (3.7 Static Random Access Memory) (11). Jedec/waffle trays are built in compliance with JEDEC thick and thin standard dimensions. The following table lists the characteristics of these types. One hot issue is the development of lead-free packages that do not suffer from the tin whiskers problem that reappeared since the recent ban on lead content. Committee(s): JC-11.2. Very small outline package (VSOP): even smaller than QSOP; 0.4-, 0.5-, or 0.65-mm pin … JC-15: Thermal Characterization Techniques for Semiconductor Packages; JC-16: Interface Technology; JC-40: Digital Logic; JC-42: Solid State Memories; JC-45: DRAM Modules; JC-63: Multiple Chip Packages; JC-64: Embedded Memory Storage & Removable Memory Cards; JC-70: Wide Bandgap Power Electronic Conversion Semiconductors; News News; JEDEC Awards: 2020 Honorees Standard Tray Dimension by JEDEC is 322.6 x 136mm (12.7 x 5.35 inches) There are 2 standard JEDEC tray thicknesses: 1. TO-220 packages have three leads. ... Obviously different SMT packages are used for different types of components, but the fact that there are standards enables activities such as printed circuit board design to be simplified as standard pad sizes and outlines can be prepared and used. ... Additional types of IC Package styles. Global Standards for the Microelectronics Industry, The latest industry news delivered right to your inbox - Free! EIA/JEDEC standards identify testing requirements that range from general to specific. Picture 2: Tube Package. Apply JC-10: Terms, Definitions, and Symbols filter, Apply JC-11: Mechanical Standardization filter, Apply JC-14: Quality and Reliability of Solid State Products filter, Apply JC-15: Thermal Characterization Techniques for Semiconductor Packages filter, Apply JC-22: Diodes and Thyristors filter, Apply JC-63: Multiple Chip Packages filter, Apply JC-64: Embedded Memory Storage & Removable Memory Cards filter, Apply JC-70: Wide Bandgap Power Electronic Conversion Semiconductors filter, Apply MO- (Microelectronic Outlines) filter, Apply MODULE (4, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7 Modules) filter, Apply MS- (Microelectronic Standards) filter, Apply SPD (4.1.2 Serial Presence Detect) filter, Apply SPP- (Standard Practices and Procedures) filter, Apply SDRAM (3.11 Synchronous Dynamic Random Access Memory) filter, Wide Bandgap Power Semiconductors: GaN, SiC, Order JEDEC Standard Manufacturer's ID Code, JC-14: Quality and Reliability of Solid State Products, JC-15: Thermal Characterization Techniques for Semiconductor Packages, JC-64: Embedded Memory Storage & Removable Memory Cards, JC-70: Wide Bandgap Power Electronic Conversion Semiconductors, JEDEC Awards: Dr. Joo Sun Choi, Samsung Electronics, JEDEC Quality & Reliability Task Group in China, JC-10: Terms, Definitions, and Symbols (17), JC-14: Quality and Reliability of Solid State Products (153), JC-15: Thermal Characterization Techniques for Semiconductor Packages (17), JC-64: Embedded Memory Storage & Removable Memory Cards (28), JC-70: Wide Bandgap Power Electronic Conversion Semiconductors (2), MODULE (4, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7 Modules) (119), SPP- (Standard Practices and Procedures) (25), SDRAM (3.11 Synchronous Dynamic Random Access Memory) (16), TEMPERATURE GRADE AND MEASUREMENT SPECIFICATIONS FOR COMPONENTS AND MODULES, Addendum No. 1, SYMBOL AND LABEL FOR ELECTROSTATIC SENSITIVE DEVICES, UNIVERSAL FLASH STORAGE (UFS), Version 3.1. Various package types options available. Axial-Through-Hole. The MAP-molded, sawn type is the standard for NXP's packages. The "TO" designation stands for "transistor outline". A notable characteristic is a metal tab with a hole, used in mounting the case to a heatsink, allowing the … All Rights Reserved. For other assistance, including website or account help, contact JEDEC by email here. CDIP SB Side-Braze Ceramic Dual In-Line Package CPGA Ceramic Pin Grid Array CZIP Ceramic Zig-Zag Package DFP Dual Flat Package There are three common MELF package sizes: MicroMELF, MiniMELF and MELF. JEDEC seal. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Glass and plastic packages. Because of the number of variables it is not possible to provide a single reflow profile that is representative of every board using a specific package type. Trays are used for shipment and handling SMD packages. Global Standards for the Microelectronics Industry, Standards & Documents Assistance:Email Julie Carlson. BGAs are available in a variety of types, ranging from plastic overmolded BGAs called PBGAs, to flex tape BGAs (TBGAs), high thermal metal top BGAs with low profiles (HL-PBGAs), and high thermal BGAs (H-PBGAs). Tray’s advantage in regards to tube packages is that they protect balls and leads from mechanical and electrical damage. A small outline transistor (SOT) is a family of small footprint, discrete surface mount transistor commonly used in consumer electronics.The most common SOT are SOT23 variations, also manufacturers offer the nearly identical thin small outline transistor (TSOT) package, where … tion cycle time and can also be used in few-chip-package (FCPs) and multi-chip modules (MCMs) configurations. TO stands for "Transistor Outline" and relates to a series of technical drawings produced by JEDEC. JEDEC also developed a number of popular package drawings for semiconductors such as TO-3, TO-5, etc. JEDEC JESD 51-5 Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms ... specification provides additional design detail for use in developing thermal test boards with application to these package types. Copyright © 2021 JEDEC. For solder practice, training and machine evaluation. DO dummy devices conform to JEDEC standards. Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick: MO-345A : Oct 2020: Standard - Plastic Dual Small Outline (SO) Gull Wing, 1.27 mm Pitch Package: MS-012G.02 : Sep 2020: Registration - Plastic Dual Small Outline Gull Wing Package, 1.45 mm Thick: MO-178D : Sep 2020: Registration - 12 Pin UFS Card, 0.91 mm Pitch 3.3 Package design Figure 4 shows a cross-section of a typical sawn QFN/SON. In electronics, TO-3 is a designation for a standardized metal semiconductor package used for power semiconductors, including transistors, silicon controlled rectifiers, and, integrated circuits. For example, all plastic package testing must follow general guidelines specified by JESD 47, but only certain types of device packages may be required to undergo HAST testing. Tray. PACKAGE INFORMATION 1. Full range from DO-7 to DO-215, View All Axial Types. Reflow profiles are dependent on numerous factors including package type, number of components, board layers, board size, reflow oven accuracy and process and more. JEDEC SMT package standards. Typically manufacturing houses have reflow profiles in place and modify them for specific hardware. Diodes' Package Outlines and Pad Layouts. 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